In general, when a semiconductor memory device is increased in integration density, a prolonged time period is consumed to write a data bit in one of the memory cells. Attempts had been made to lessen the time period consumed for write-in operation. One of such attempts is to concurrently write a plurality of data bytes during a single write-in operation, which is sometimes referred to as "page write-in function", and the page write-in function is widely applied to the semiconductor memory devices.
A typical example of the semiconductor memory device is illustrated in FIG. 1 of the drawings, and a data bit is electrically erasable and written into the memory cell of the semiconductor memory device. Then, the semiconductor memory device is of the EEPROM (Electrically Erasable Programmable Read Only Memory) type. The semiconductor memory device shown in FIG. 1 largely comprises 256 row address lines X1 to X256, 32 column address lines Y1 to Y32, and a memory cell array 1 the memory cells of which are grouped into 8192 bytes. However, only four memory cell groups 2, 3, 4 and 5 are illustrated in detail and the four memory cell groups 2, 3, 4 and 5 are located at four corners of the memory cell array 1, respectively. Then, address locations of first, thirty second, eight thousand one hundred and sixty first and eight thousand one hundred and ninety second bytes are respectively assigned to the four memory cell groups 2, 3, 4 and 5, respectively. Each memory cell group is provided with eight memory cells for memorizing a byte of data bits. All of the memory cell groups are identical in circuit arrangement with one another, so that description is made for the memory cell group 2 only and other memory cells are omitted from the following description as if no other memory cell is incorporated. However, transistors and signal lines of another memory cell group are hereinunder mentioned by reference names with a combination of numerals assigned to the row address line, the column address line and a bit location, if necessary. For example, transistors gated by the column address line Y32 are labeled by Qy.sub.321 to Qy.sub.328, because these transistors are related to the column address line Y32 and the first to eighth bit locations.
The memory cell group 2 comprises eight memory cell transistors Mm.sub.111 to Mm.sub.118 respectively accompanied by eight memory cell selecting transistors Ms.sub.111 to Ms.sub.118 and a row address selecting transistor Mb.sub.11, and each of the memory cell transistors is of an n-channel floating gate type. The row address selecting transistors and the memory cell selecting transistors are formed by n-channel type field effect transistors. Each n-channel type field effect transistor is indicated by an arrow drawn from the source node thereof, but each p-channel type field effect transistor is indicated by an arrow toward the source node thereof. The row address line X1 is commonly coupled to not only the gate electrodes of the memory cell selecting transistors Ms.sub.111 to Ms.sub.118 but also the gate electrode of the row address selecting transistor Mb.sub.11. On the other hand, the column address line Y1 is shared by column address selecting transistors Qy.sub.11 to Qy.sub.18 which are respectively provided in association with the memory cells, and the column address selecting transistors Qy.sub.11 to Qy.sub.18 are coupled at the source nodes thereof to the drain nodes of the memory cell selecting transistors Ms.sub.111 to Ms.sub.118, respectively. The column address selecting transistor Qy.sub.11 is gated by the write-in controlling line di.sub.11 and turns off to prevent a sense amplifier SA1 and non-selected memory cell groups from the write-in and erasing operations upon selection. The row address selecting transistor Mb.sub.11 is associated with a byte column selecting transistor Qg.sub.1 which has a gate electrode coupled to a byte column selecting line Y.sub.1b. The byte column selecting transistor Qg.sub.1 is then gated by the byte column selecting line Y.sub.b1 and propagates a control signal for supplying the row address selecting transistor Mb.sub.11 therewith. The memory cell selecting transistors Ms.sub.111 to Ms.sub.118 are further coupled at the drain nodes thereof to the source nodes of the write-in transistors Qd.sub.11 to Qd.sub.18, respectively, and the write-in transistors Qd.sub.11 to Qd.sub.18 have respective gate electrodes coupled to write-in controlling lines di.sub.11 to di.sub.18. All of the memory cell transistors Mm.sub.111 to Mm.sub.118 are commonly coupled to a source voltage controlling circuit 7. The byte column selecting transistor Qg.sub.1 propagates the control signal Vcg or blocks it depending upon the voltage level of the byte column selecting line Y.sub.1b, and the write-in transistors Qd.sub.11 to Qd.sub.18 are respectively activated by the write-in controlling lines di.sub.11 to di.sub.18 to supply the memory cell selecting transistors Ms.sub.111 to Ms.sub.118, respectively, with a write-in voltage Vwr.
Now, a write-in operation is described for the memory cell groups 2 and 3 assigned the first byte and the thirty second byte. However, the memory cells except for these forming part of the memory cell groups 2 and 3 are ignored in the following description for the sake of simplicity. Each write-in operation is divided into a loading phase followed by an automatically erasing phase and a write-in phase. In the loading phase, memory cell groups are selected from the memory cell array, and logic levels are decided on the basis of write-in data bits. The data bits stored in the memory cell groups 2 and 3 are concurrently erased in the automatically erasing phase next to the loading phase, and the write-in data bits are finally written into the selected memory cell groups in the write-in phase. The control signal Vcg has a write-in/erasing level Vpp during the automatically erasing phase and is shifted to a read-out level of about 1 volt in a read-out operation. However, the control signal Vcg is recovered to the ground level when the semiconductor memory device enters another phase. On the other hand, the write-in voltage Vwr stays in the ground level in both loading and automatically erasing phases. However, the write-in voltage Vwr is shifted to the write-in/erasing level Vpp during the write-in phase. The source voltage controlling circuit 7 is responsive to a write-in signal WR which goes up to a positive voltage level Vcc during the write-in phase only. When the write-in signal WR goes up to positive voltage level Vcc, n-channel type field effect transistors Qs2 and Qs3 turn on but a p-channel type field effect transistor Qs1 and an n-channel type field effect transistor Qs4 remain off. Then, a source voltage Vs goes up to a positive voltage level of "Vcc-Vth" where Vth is the threshold voltage of the n-channel type field effect transistor Qs3. However, the source voltage Vs remains in the ground level during the loading and automatically erasing phases due to the write-in signal of the ground level.
Turning to FIG. 2, there is shown a data input circuit 8 which produces the write-in controlling signals di.sub.11 to di.sub.328. The data input circuit 8 is provided with eight input blocks Di1 to Di8, and each input block produces 32 write-in controlling signals respectively corresponding to 32 columns of the memory cells each selected from each of the memory cell groups. All of the input blocks Di1 to Di8 are similar in circuit arrangement, so that description is focused upon the input block Di1 only. The input block Di1 comprises a latching circuit 9, thirty two gate transistors Qt.sub.1 to Qt.sub.32 respectively controlled by the column address lines Y1 to Y32, and thirty two high-voltage latching circuits Lt.sub.1 to Lt.sub.32. The latching circuit 9 is responsive to a latching signal DL and the inverting signal thereof to store an input data bit I1 which is transferred to one of the high-voltage latching circuits through one of the gate transistors depending upon the selected column address line. Thus, the input data bit I1 is stored by one of the high-voltage latching circuits, and the high-voltage latching circuit produces a high voltage write-in control signal supplied to the write-in controlling line.
The latching circuit 9 is illustrated in detail in FIG. 3 of the drawings. The latching circuit 9 comprises a first transfer gate 10, a series combination of inverter circuits 11 and 12 coupled to the first transfer gate 10 and a second transfer gate 13 coupled in parallel to the series combination of the inverter circuits 11 and 12. The first transfer gate 10 is provided with a p-channel enhancement type field effect transistor Ql.sub.1 and an n-channel enhancement type field effect transistor Ql.sub.2, and the second transfer gate 13 is also provided with a p-channel enhancement type field effect transistor Ql.sub.3 and an n-channel enhancement type field effect transistor Ql.sub.4. The latching signal DL and the inverting signal thereof are respectively supplied to the n-channel enhancement transistor Ql.sub.2 and the p-channel enhancement transistor Ql.sub.1 for the first transfer gate and to the p-channel enhancement type field effect transistor Ql.sub.3 and the n-channel enhancement type field effect transistor Ql.sub.4, so that the first and second transfer gates 10 and 13 are complementarily shifted between on states and off states. As a result, when the latching signal DL goes up to the high level, the input data bit I1 passes through the first transfer gate 10 and is, accordingly, latched in the series combination of the inverter circuits 11 an 12. Subsequently, the latching signal DL goes down to the low level, then the first transfer gate 10 turns off but the second transfer gate 13 turns on to retain the input data bit I1.
The circuit arrangement of the high-voltage latching circuit Lt.sub.1 is illustrated in detail in FIG. 4 of the drawings. The high-voltage latching circuit Lt.sub.1 comprises two high-voltage inverter circuits 14 and 15 coupled in series and a bypassing path 16 coupled in parallel to the high-voltage inverter circuits 14 and 15. Each of the high-voltage inverter circuits 14 and 15 is provided with a p-channel enhancement type field effect transistor Qh.sub.1 or Qh.sub.3 and an n-channel enhancement type field effect transistor Qh.sub.2 or Qh.sub.4. Each p-channel enhancement type field effect transistors Qh.sub.1 or Qh.sub.3 is formed in an n-well supplied with a biasing signal Vpp', and the biasing signal Vpp' is in the positive voltage level Vcc during the loading phase. However, the biasing signal Vpp' goes up to the write-in/erasing level Vpp when the semiconductor memory device is shifted to the automatically erasing phase or the write-in phase. Each of the component transistors Qh.sub.3 and Qh.sub.4 is sufficiently small in gate width/gate length ratio with respect to the corresponding component transistor of the inverter circuit 12, so that the write-in control signal on the write-in control line di.sub.11 is varied in voltage level depending upon the voltage level of the input data bit. Namely, when the input data bit I1 of the high level is supplied to the high-voltage inverter circuit 14, the n-channel enhancement type field effect transistor Qh.sub.2 turns on to cause a node 16 to have the ground level which allows the n-channel enhancement type field effect transistor Qh.sub.4 to remain off. This results in the positive voltage level Vcc on the write-in/erasing line di.sub.11 which is fed back to the high-voltage inverter circuit 14, thereby allowing the node 16 to memorize the input data bit di.sub.11. In this situation, if the biasing signal Vpp' goes up from the positive voltage level Vcc to the write-in/erasing level Vpp, the write-in control line di.sub.11 follows the biasing signal Vpp', thereby rising from the positive voltage level Vcc to the write-in/erasing level Vpp. On the other hand, if the input data bit of the low level is supplied to the high-voltage inverter circuit 14, the node 16 goes up to the positive voltage level Vcc by tuning the p-channel enhancement type field effect transistor Qh.sub.1 on. Then, the n-channel enhancement type field effect transistor Qh.sub.4 turns on to causing the write-in/erasing line di.sub.11 to remain in the ground level. In this situation, the write-in/erasing line di.sub.11 is kept in the ground level even if the biasing voltage goes up from the positive voltage level Vcc to the write-in/erasing level Vpp.
Turning to FIG. 5 of the drawings, there is shown a column address decoder circuit 17 which activates the column address line Y1 for gating the column address selecting transistors Qy.sub.11 to Qy.sub.18. The column address decoder circuit 17 is provided for the column address line Y1, but other groups of column address selecting transistors are associated with other column address decoder circuits, respectively. The column address decoder circuit 17 comprises a NAND gate 18 and a NOR gate 19 provided with two p-channel enhancement type field effect transistors 20 and 21 and two n-channel enhancement type field effect transistors 22 and 23. A set of address signal lines 24 are coupled in parallel to the input nodes of the NAND gate 18, and the NOR gate 19 are coupled at the two input nodes thereof to the output node of the NAND gate 18 and a write-in/erasing controlling signal WRITE, respectively. The column address decoder circuit 17 thus arranged is operative to drive the column address line Y1 which are shared by the column address selecting transistors Qy.sub.11 to Qy.sub.18 as shown in FIG. 1. Namely, the write-in/erasing controlling signal goes up to the positive voltage level Vcc during the automatically erasing phase and the write-in phase, and, for this reason, the column address line Y1 remains in the ground level due to the n-channel enhancement type field effect transistor 23 in the on-state. However, the write-in/erasing controlling signal WRITE is shifted to the ground level upon entrance into the loading phase, so that the NOR gate 19 is responsive to the level at the output node of the NAND gate 18. When the column address lines 24 specify the column address decoder circuit 17, the NAND gate 18 produces the low level which allows the p-channel enhancement type field effect transistor 21 to turn on to drive the column address line Y1 to the positive voltage level Vcc. However, the other column address decoder circuits have the respective NAND gates each having the output node in the positive voltage level Vcc, then the respective NOR gates of the decoder circuits produce the respective low voltage levels, thereby allowing the other column address lines to remain in the inactive levels, respectively.
In FIGS. 6 and 7 of the drawings, there is shown a byte column selecting circuit 25 which drives the byte column selecting line Y.sub.1b. Though not shown in the drawings, each byte column selecting line is associated with each byte column selecting circuit. The byte column selecting circuit 25 comprises NAND gates 26 and 27, a high-voltage switching circuit 28, an inverter circuit 29 and a latching circuit 30. The NAND gate 27 is provided with two p-channel enhancement type field effect transistors 31 and 32 coupled to the NAND gate 26 and the high-voltage switching circuit 28, respectively, two n-channel enhancement type field effect transistors 33 and 34 respectively coupled to the NAND gate 26 and the high-voltage switching circuit 28 and an n-channel depletion type field effect transistor 35. The inverter circuit 29 has a series combination of a p-channel enhancement type field effect transistor 36 and an n-channel enhancement type field effect transistor 37. The latching circuit 30 comprises two series combinations of p-channel enhancement type field effect transistors 38, 39, 40 and 41, and four n-channel enhancement type field effect transistors 42, 43, 44 and 45, and the high-voltage switching circuit 28 comprises p-channel enhancement type field effect transistors 46, 47 and 48 each formed in an n-type well supplied with the biasing signal Vpp', two n-channel enhancement type field effect transistors 49 and 50, and an inverter circuit 51. The address signal lines 24 are coupled to the input nodes of the NAND gate 26, and the NAND gate 26 produces the low level at the output node thereof if the address signal lines 24 specify the leftmost byte column of the memory cell array 1. However, the high level takes place if the address signal lines 24 specify another byte column. Then, the byte column selecting circuit 25 is specified by the address signal lines 24, the low voltage level is produced at the output node thereof which is inverted by the inverter circuit 29 to allow an output node 52 to go up to the positive voltage level Vcc. This results in that a node 53 goes down to the ground level by turning the n-channel enhancement type field effect transistor 42 on. However, a complementary node 54 has the positive voltage level Vcc because a conduction path is formed through the p-channel enhancement type field effect transistors 40 and 41 under a resetting signal RESET of an inactive the ground level. The complementary node 54 causes the p-channel type enhancement type field effect transistor 38 to be turned off in so far as the resetting signal RESET remains in the inactive the ground level, so that the node 53 keeps the ground level even if the node 52 is shifted to the positive voltage level Vcc. Thus, the positive voltage level Vcc at the node 52 is memorized in the latching circuit 30 until the resetting signal RESET is shifted to the high level. With the positive voltage level Vcc at the complementary node 54, the n-channel enhancement type field effect transistor 49 turns on but the n-channel enhancement type field effect transistor 50 turns off because the inverse produced by the inverter circuit 51 is supplied thereto. Then, a node 55 and a complementary node 56 have the ground level and the positive voltage level Vcc, respectively, which are allowed to stay therein by the functions of the p-channel enhancement type field effect transistor 47 of off-state and the p-channel enhancement type field effect transistor 48 of on-state. Since the biasing signal Vpp' remains in the positive voltage level Vcc during the loading phase, the nodes 55 and 56 are unchanged in voltage level. However, the biasing signal Vpp' has the write-in/erasing level Vpp during the automatically erasing and write-in phases, so that the node 55 is boosted up to the write-in/erasing level Vpp which is causative of boosting up the byte column selecting line Y.sub.1b toward the write-in/erasing level Vpp. On the other hand, when the address signal lines 24 do not specify the leftmost byte column, the NAND gate 26 produces the high level at the output node thereof, then causing the node 52 to remain in the ground level. The ground level is memorized into the latching circuit 30, and the node 55 and the complementary node 56 are respectively shifted to the positive voltage level Vcc and the ground level which are kept during the loading phase. In the automatically erasing and write-in phases, the byte column selecting line Y.sub.1b goes down to the ground level, because a conduction path takes place from the byte column selecting line Y.sub.1b through the field effect transistors 35, 33 and 34 to the ground due to the high level produced by the inverter circuit 51.
An example of the page write-in function is described with reference to FIG. 8 on the assumption that two bytes of data bits (10101010) and (01010101) are supplied to the semiconductor memory device for writing them into the memory cell groups 2 and 3, respectively.